Researchers on the
IEEE Digital Elements and Expertise Convention (ECTC) final week pushed the cutting-edge in a expertise that’s changing into vital to cutting-edge processors and reminiscence. Referred to as hybrid bonding, the expertise stacks two or extra chips atop one another in the identical bundle, permitting chipmakers to extend the variety of transistors of their processors and recollections regardless of a basic slowdown within the tempo of the standard transistor shrinking that after outlined Moore’s Regulation. Analysis teams from main chipmakers and universities demonstrated a wide range of hard-fought enhancements, with a number of—together with from Utilized Supplies, Imec, Intel, and Sony—displaying outcomes that might result in a document density of connections between 3D stacked chips of round 7 million hyperlinks in a sq. millimeter of silicon.
All these connections are wanted due to the brand new nature of progress in semiconductors, Intel’s
Yi Shi informed engineers at ECTC. As Intel basic supervisor of expertise improvement Ann Kelleher defined to IEEE Spectrum in 2022, Moore’s Regulation is now ruled by an idea known as system expertise co-optimization, or STCO. In STCO, a chip’s capabilities, akin to cache reminiscence, enter/output, and logic are separated out and made utilizing the perfect manufacturing expertise for every. Hybrid bonding and different superior packaging tech can then reassemble them in order that they work like a single piece of silicon. However that may solely occur with a excessive density of connections that may shuttle bits between items of silicon with little delay or vitality consumption.
Hybrid bonding isn’t the one superior packaging expertise in use, but it surely gives the best density of vertical connections. And it dominated ECTC, making up about one-fifth of the analysis introduced, in line with
Chris Scanlan, senior vice chairman of expertise at Besi, whose instruments have been behind a number of of the breakthroughs.
“It’s tough to say what would be the restrict. Issues are shifting very quick.”
—Jean-Charles Souriau, CEA Leti
In hybrid bonding, copper pads are constructed on the high face of every chip. The copper is surrounded by insulation, normally silicon oxide, and the pads themselves are barely recessed from the floor of the insulation. After the oxide is chemically modified, the 2 chips are then pressed collectively face-to-face, so the recessed pads align with every. This sandwich is then slowly heated, inflicting the copper to broaden throughout the hole, connecting the 2 chips.
Hybrid bonding can both connect particular person chips of 1 measurement to a wafer filled with chips of a bigger measurement or used to bond two full wafers of chips of the identical measurement collectively. Thanks partly to its use in digital camera chips, the latter is a extra mature course of than the previous. Imec, for instance, reported a few of the
most dense wafer-on-wafer (WoW) bonds ever with a bond-to-bond distance (or pitch) of simply 400 nanometers. The identical analysis heart managed a 2-micrometer pitch for the chip-on-wafer (CoW) state of affairs. (Industrial chips in the present day have connections about 9 μm aside.)
Hybrid bonding begins by forming recessed copper pads on the high of the chip [top]. The encircling oxide dielectric bonds when the 2 chips are pressed collectively [middle]. Annealing expands the copper to kind a conductive connection [bottom].
“With the tools out there, it’s simpler to align wafer to wafer than chip to wafer. Most processes for microelectronics are made for [full] wafers,” says
Jean-Charles Souriau, scientific chief in integration and packaging on the French analysis group, CEA Leti. Nevertheless, it’s chip-on-wafer (or die-to-wafer) that’s making a splash in high-end processors akin to AMD’s Epyc line, the place the approach is used to assemble compute cores and cache reminiscence in its superior CPUs and AI accelerators.
In pushing for tighter and tighter pitches for each situations, researchers centered on making surfaces fractionally flatter, getting certain wafers to stay collectively higher, and reducing the time and complexity of the entire course of. Getting it proper may in the end imply enabling a revolution in how chips are designed.
WoW, these are some tight pitches
The wafer-on-wafer (WoW) analysis that reported the tightest pitches—500 nm to 360 nm—all spent a number of effort on one factor: flatness. To bind two wafers along with 100-nm-level accuracy, the entire wafer must be practically completely flat. If it’s bowed or warped, complete sections of the supplies received’t join.
Flattening wafers is the job of a course of known as chemical mechanical planarization, or CMP. It’s key to chipmaking usually, particularly for the components of the method that produce the layers of interconnects above the transistors.
“CMP is a key parameter we’ve got to manage for hybrid bonding,” says Souriau. Outcomes introduced this week at ECTC took CMP to a different degree, not simply flattening throughout the wafer however lowering mere nanometers of roundness on the insulation between the copper pads to make sure higher connections.
Different analysis centered on guaranteeing these flattened components caught collectively strongly sufficient by experimenting with totally different floor supplies akin to silicon carbonitride as a substitute of silicon oxide or through the use of totally different schemes to chemically activate the floor. Initially, when wafers or dies are pressed collectively, they’re held in place with comparatively weak hydrogen bonds, and the priority is guaranteeing that all the things stays in place between the bonding and additional steps. Certain wafers and chips are then heated slowly (a course of known as annealing) to kind stronger chemical bonds. Simply how robust these bonds are—and how one can even determine that out—was the topic of a number of analysis at ECTC.
A part of that closing bond power would come from the copper connections as properly. The annealing step expands the copper throughout the hole to kind a conductive bridge. Controlling the dimensions of that hole is vital, defined Samsung’s
Seung Ho Hahn. An excessive amount of of a niche and the copper received’t join. Too little and it’ll push the wafers aside. It’s a matter of nanometers, and Hahn reported analysis on a brand new chemical course of that hopes to get it excellent by etching away the copper a single atomic layer at a time.
The standard of the connection counts, too. Even after the copper expands, most schemes confirmed that the steel’s grain boundaries don’t cross from one facet to a different. Such a crossing reduces a connection’s electrical resistance and may enhance its reliability. Researchers at Tohoku College in Japan reported a brand new metallurgical scheme that might lastly generate giant, single grains of copper that cross the boundary. “This can be a drastic change,” mentioned
Takafumi Fukushima, an affiliate professor at Tohoku College. “We are actually analyzing what underlies it.”
“I believe it’s attainable to make greater than 20-layer stack utilizing this expertise.”
—Hyeonmin Lee, Samsung
Different experiments centered on streamlining the hybrid bonding course of. A number of sought to scale back the annealing temperature wanted to kind bonds—sometimes round 300 °C—motivated by the potential to scale back any danger of injury to the chips from the extended heating. And researchers from
Utilized Supplies introduced progress on a way to radically scale back the time wanted for annealing—from hours to simply 5 minutes.
CoWs which can be excellent within the area
Chip-on-wafer (CoW) hybrid bonding is extra helpful to trade in the intervening time: It permits chipmakers to stack chiplets of various sizes collectively, and to check every chip earlier than it’s certain to a different, guaranteeing that they aren’t fatally dooming an costly CPU with a single flawed half.
However CoW comes with the entire difficulties of WoW and fewer of the choices to alleviate them. For instance, CMP is designed to flatten wafers, not particular person dies. As soon as dies have been reduce from their supply wafer and examined, there’s much less that may be executed to enhance their readiness for bonding.
Nonetheless, Intel reported CoW hybrid bonds with a 3-μm pitch, and Imec managed 2 μm, largely by making the transferred dies very flat whereas they have been nonetheless hooked up to the wafer and maintaining them additional clear going ahead. Efforts by each teams used plasma etching to cube up the dies as a substitute of the same old technique, which makes use of a specialised blade. Plasma received’t result in chipping on the edges, which creates particles that interferes with connections. It additionally allowed the Imec group to form the die, making
chamfered corners that relieved mechanical stress that might break connections.
CoW hybrid bonding goes to be vital to the way forward for high-bandwidth reminiscence (HBM), a number of researchers informed
IEEE Spectrum. HBM is a stack of DRAM dies atop a management logic chip—at present 8 to 12 dies excessive. Typically positioned throughout the similar bundle as high-end GPUs, HBM is essential to offering the tsunami of information wanted to run giant language fashions like ChatGPT. At the moment, HBM dies are stacked utilizing so-called microbump expertise, during which tiny balls of solder between every layer are surrounded by an natural filler.
However with AI pushing reminiscence demand even greater, DRAM makers need to do 20 layers or extra in HBM chips. Nevertheless, the quantity microbumps take up imply that these stacks will quickly be too tall to slot in the bundle with GPUs. Hybrid bonding wouldn’t simply shrink the peak of HBMs, it also needs to make it simpler to take away extra warmth from the bundle, as a result of there may be much less thermal resistance between its layers.
A 200-nanometer WoW pitch isn’t just attainable, however fascinating.
At ECTC, Samsung engineers confirmed {that a} hybrid bonding scheme may make a 16-layer HBM stack. “I believe it’s attainable to make greater than 20-layer stack utilizing this expertise,” mentioned
Hyeonmin Lee, a senior engineer at Samsung.
Different new CoW expertise may assist deliver hybrid bonding to high-bandwidth reminiscence. Although they didn’t current analysis on this at ECTC, researchers at
CEA Leti are engaged on so-called self-alignment expertise, says Souriau. That might assist guarantee CoW connections utilizing chemical processes. Some components of every floor could be made hydrophobic and a few hydrophilic, leading to surfaces that will slide into place robotically.
At ECTC, researchers at Tohoku College and Yamaha Robotics reported work on an analogous scheme, utilizing the floor stress of water to align 5-μm pads on experimental DRAM chips with higher than 50-nm accuracy.
How far can hybrid bonding go?
Researchers will nearly actually hold pushing the pitch of hybrid bonding connections. A 200-nm WoW pitch isn’t just attainable however fascinating,
Han-Jong Chia, a program supervisor pathfinding techniques at Taiwan Semiconductor Manufacturing Co., informed engineers at ECTC. Inside two years, TSMC plans to introduce a expertise known as bottom energy supply. (Intel plans it for the tip of this 12 months.) That’s a expertise that places the chip’s chunky power-delivery interconnects beneath the silicon as a substitute of above it. With these out of the way in which, the uppermost interconnect ranges can join higher to smaller hybrid bonding bond pads, TSMC researchers calculate. Again facet energy supply with 200-nm bond pads would reduce down the capacitance of 3D connections a lot that the product of vitality effectivity and sign delay could be as a lot as 9 instances as excessive as what might be achieved with 400-nm bond pads.
Sooner or later sooner or later, if bond pitches are narrowed even additional, Chia recommended, it’d change into sensible to “fold” blocks of circuitry so they’re constructed throughout two wafers. That means a few of the longer connections throughout the block is perhaps made shorter by the vertical pathway, probably dashing computations and decreasing energy consumption.
And hybrid bonding is probably not restricted to silicon. “At the moment there may be a number of improvement in silicon-to-silicon wafers, however we’re additionally seeking to do hybrid bonding between gallium nitride and silicon wafers and glass wafers…all the things on all the things,” says CEA Leti’s Souriau. His group even introduced analysis on hybrid bonding for quantum-computing chips, which includes aligning and binding superconducting niobium as a substitute of copper.
“It’s tough to say what would be the restrict,” Souriau says. “Issues are shifting very quick.”
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